JPS6138510B2 - - Google Patents

Info

Publication number
JPS6138510B2
JPS6138510B2 JP55024369A JP2436980A JPS6138510B2 JP S6138510 B2 JPS6138510 B2 JP S6138510B2 JP 55024369 A JP55024369 A JP 55024369A JP 2436980 A JP2436980 A JP 2436980A JP S6138510 B2 JPS6138510 B2 JP S6138510B2
Authority
JP
Japan
Prior art keywords
data
mar
line
cells
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55024369A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56121138A (en
Inventor
Etsuo Masuda
Yukio Nakamura
Akihiko Doi
Hiroshi Fujita
Chikayoshi Hosokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP2436980A priority Critical patent/JPS56121138A/ja
Publication of JPS56121138A publication Critical patent/JPS56121138A/ja
Publication of JPS6138510B2 publication Critical patent/JPS6138510B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Memory System (AREA)
  • Communication Control (AREA)
JP2436980A 1980-02-28 1980-02-28 Buffer memory controlling system Granted JPS56121138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2436980A JPS56121138A (en) 1980-02-28 1980-02-28 Buffer memory controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2436980A JPS56121138A (en) 1980-02-28 1980-02-28 Buffer memory controlling system

Publications (2)

Publication Number Publication Date
JPS56121138A JPS56121138A (en) 1981-09-22
JPS6138510B2 true JPS6138510B2 (en]) 1986-08-29

Family

ID=12136268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2436980A Granted JPS56121138A (en) 1980-02-28 1980-02-28 Buffer memory controlling system

Country Status (1)

Country Link
JP (1) JPS56121138A (en])

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62182405U (en]) * 1986-05-09 1987-11-19

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58161038A (ja) * 1982-03-19 1983-09-24 Fujitsu Ltd バツフア管理方式
JPS6091482A (ja) * 1983-10-24 1985-05-22 Fujitsu Ltd メモリ管理方式
JPH0666988B2 (ja) * 1985-03-29 1994-08-24 株式会社日立製作所 加入者デ−タ制御方法
JPS6319939A (ja) * 1986-07-14 1988-01-27 Fujitsu Ltd 通信制御装置
JP2938732B2 (ja) 1993-11-10 1999-08-25 松下電送システム株式会社 メモリ管理装置とこれを用いたファクシミリ装置
US7159122B2 (en) * 2003-05-12 2007-01-02 International Business Machines Corporation Message digest instructions
US7257718B2 (en) 2003-05-12 2007-08-14 International Business Machines Corporation Cipher message assist instructions
US7356710B2 (en) 2003-05-12 2008-04-08 International Business Machines Corporation Security message authentication control instruction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62182405U (en]) * 1986-05-09 1987-11-19

Also Published As

Publication number Publication date
JPS56121138A (en) 1981-09-22

Similar Documents

Publication Publication Date Title
US5031091A (en) Channel control system having device control block and corresponding device control word with channel command part and I/O command part
KR100638067B1 (ko) 고성능 통신 제어기
EP1026596B1 (en) Direct memory access control
KR100268565B1 (ko) 다중 처리 시스템에서 타스크를 큐잉하기 위한 시스템 및 방법
CA1100643A (en) Microprocessor architecture with integrated interrupts and cycle steals prioritized channel
US4956771A (en) Method for inter-processor data transfer
US7363389B2 (en) Apparatus and method for enhanced channel adapter performance through implementation of a completion queue engine and address translation engine
US4860244A (en) Buffer system for input/output portion of digital data processing system
US5315708A (en) Method and apparatus for transferring data through a staging memory
EP2097828B1 (en) Dmac to handle transfers of unknown lengths
US20040225779A1 (en) Programmable CPU/interface buffer structure using dual port RAM
GB1597202A (en) Communications processor architecture
JP2001216194A (ja) 演算処理装置
US4040037A (en) Buffer chaining
US5608889A (en) DNA controller with wrap-around buffer mode
JPS6138510B2 (en])
US5896549A (en) System for selecting between internal and external DMA request where ASP generates internal request is determined by at least one bit position within configuration register
EP1026597A2 (en) Data alignment between buses
JPH07225727A (ja) 計算機システム
US7475170B2 (en) Data transfer device for transferring data to and from memory via a bus
CN104050111A (zh) 通过具有不同时序要求的相应命令访问不同类型的存储器
US5765041A (en) System for triggering direct memory access transfer of data between memories if there is sufficient data for efficient transmission depending on read write pointers
EP0290942B1 (en) Guest machine execution control system for virtual machine system
US5872962A (en) Program control system
US5432910A (en) Coupling apparatus and method for increasing the connection capability of a communication system